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ST72589BW 데이터시트(PDF) 97 Page - STMicroelectronics |
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ST72589BW 데이터시트(HTML) 97 Page - STMicroelectronics |
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97 / 158 page ![]() ST72589BW, ST72389BW 97/158 SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (ERPR) Read/Write Reset Value: 0000 0000 (00 h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Pres- caler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 3.) is divided by the binary factor set in the ERPR register (in the range 1 to 255). The extended baud rate generator is not used af- ter a reset. EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (ETPR) Read/Write Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate divi- sion factor for the transmit circuit. Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Pres- caler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 3.) is divided by the binary factor set in the ETPR register (in the range 1 to 255). The extended baud rate generator is not used af- ter a reset. 70 ERPR 7 ERPR 6 ERPR 5 ERPR 4 ERPR 3 ERPR 2 ERPR 1 ERPR 0 70 ETPR 7 ETPR 6 ETPR 5 ETPR 4 ETPR 3 ETPR 2 ETPR 1 ETPR 0 |
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