ST72589BW datasheet(30/158 Pages) STMICROELECTRONICS

30 / 158 page

ST72589BW, ST72389BW

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POWER SAVING MODES (Cont’d)

Standard HALT mode

In this mode the main oscillator is turned off caus-

ing all internal processing to be stopped, including

the operation of the on-chip peripherals. All periph-

erals are not clocked except the ones which get

their clock supply from another clock generator

(such as an external oscillator).

The HALT instruction when executed while the

Watchdog system is enabled, generates a Watch-

dog RESET.

When exiting HALT mode by means of a RESET

or an interrupt, the oscillator is immediately turned

on and the 4096 CPU cycle delay is used to stabi-

lize the oscillator.

Specific ACTIVE-HALT mode

As soon as the interrupt capability of the main os-

cillator is selected (OIE bit set), the HALT instruc-

tion will make the device enter a specific ACTIVE-

HALT power saving mode instead of the standard

HALT one.

This mode consists of having only the main oscil-

lator and its associated counter running to keep a

wake-up time base. All other peripherals are not

clocked except the ones which get their clock sup-

ply from another clock generator (such as external

oscillator).

The safeguard against staying locked in this AC-

TIVE-HALT mode is insured by the oscillator inter-

rupt.

Note: As soon as the interrupt capability of the os-

cillators is selected (OIE bit set), entering in AC-

TIVE-HALT mode while the Watchdog is active

does not generate a RESET.

This means that the device cannot to spend more

than a defined delay in this power saving mode.

Figure 19. HALT modes flow-chart

HALT INSTRUCTION

OSCILLATOR

CPU

OSCILLATOR

PERIPHERALS

I1 AND I0 BITS

OFF

Notes:

OIE BIT

CPU

OSCILLATOR

PERIPHERALS

I1 AND I0 BITS

OFF

RESET

EXTERNAL*

CPU

OSCILLATOR

PERIPHERALS

OFF

INTERRUPT

HALT

ACTIVE-HALT

MAIN

FETCH RESET VECTOR

OR SERVICE INTERRUPT**

4096 clock cycles delay

CPU

OSCILLATOR

PERIPHERALS

External interrupt or internal interrupts with Exit from Halt Mode capability

** Before servicing an interrupt, the CC register is pushed on the stack.

WATCHDOG

ENABLE

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