 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
ST72611F1 데이터시트(PDF) 54 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST72611F1 데이터시트(HTML) 54 Page - STMicroelectronics |
|
|
54 / 80 page  ST7261 54/80 11.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fCPU, and TA. 11.5.1 General Timings 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. ∆t c(INST) is the number of tCPU cycles needed to finish the current instruction execution. 11.5.2 CONTROL TIMING CHARACTERISTICS Note 1: Not tested in production, guaranteed by design. Symbol Parameter Conditions Min Typ 1) Max Unit tc(INST) Instruction cycle time fCPU=8MHz 2 3 12 tCPU 250 375 1500 ns tv(IT) Interrupt reaction time 2) tv(IT) = ∆tc(INST) + 10 tCPU fCPU=8MHz 10 22 tCPU 1.25 2.75 µs CONTROL TIMINGS Symbol Parameter Conditions Value Unit Min 1) Typ. 1) Max 1) fOSC Oscillator Frequency 12 MHz fCPU Operating Frequency 8 MHz tRL External RESET Input pulse Width 1.5 tCPU tPORL Internal Power Reset Duration 514 tCPU TRSTL Reset Pin Output Pulse Width 10 µs tWDG Watchdog Time-out fcpu = 8MHz 65536 8.192 4194304 524.288 tCPU ms tOXOV Crystal Oscillator Start-up Time 20 30 40 ms tDDR Power up rise time from VDD = 0 to 4V 100 ms |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
