전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

AT80SND1C-ROTIL 데이터시트(PDF) 15 Page - ATMEL Corporation

부품명 AT80SND1C-ROTIL
상세설명  Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
PDF  210 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  ATMEL [ATMEL Corporation]
홈페이지  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT80SND1C-ROTIL 데이터시트(HTML) 15 Page - ATMEL Corporation

Back Button AT80SND1C-ROTIL Datasheet HTML 11Page - ATMEL Corporation AT80SND1C-ROTIL Datasheet HTML 12Page - ATMEL Corporation AT80SND1C-ROTIL Datasheet HTML 13Page - ATMEL Corporation AT80SND1C-ROTIL Datasheet HTML 14Page - ATMEL Corporation AT80SND1C-ROTIL Datasheet HTML 15Page - ATMEL Corporation AT80SND1C-ROTIL Datasheet HTML 16Page - ATMEL Corporation AT80SND1C-ROTIL Datasheet HTML 17Page - ATMEL Corporation AT80SND1C-ROTIL Datasheet HTML 18Page - ATMEL Corporation AT80SND1C-ROTIL Datasheet HTML 19Page - ATMEL Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 210 page
background image
15
AT8xC51SND1C
4109E–8051–06/03
Registers
Table 16. CKCON Register
CKCON (S:8Fh) – Clock Control Register
Reset Value = 0000 000Xb (AT89C51SND1C) or 0000 0000b (AT83C51SND1C)
Table 17. PLLCON Register
PLLCON (S:E9h) – PLL Control Register
Reset Value = 0000 1000b
765
43210
-
WDX2
-
-
-
T1X2
T0X2
X2
Bit
Number
Bit
Mnemonic
Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6WDX2
Watchdog Clock Control Bit
Set to select the oscillator clock divided by 2 as watchdog clock input (X2
independent).
Clear to select the peripheral clock as watchdog clock input (X2 dependent).
5 - 3
-
Reserved
The values read from these bits are indeterminate. Do not set these bits.
2T1X2
Timer 1 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 1 clock input (X2
independent).
Clear to select the peripheral clock as timer 1 clock input (X2 dependent).
1T0X2
Timer 0 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 0 clock input (X2
independent).
Clear to select the peripheral clock as timer 0 clock input (X2 dependent).
0X2
System Clock Control Bit
Clear to select 12 clock periods per machine cycle (STD mode, F
CPU = FPER =
F
OSC/2).
Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC).
765
43210
R1
R0
-
-
PLLRES
-
PLLEN
PLOCK
Bit
Number
Bit
Mnemonic
Description
7 - 6
R1:0
PLL Least Significant Bits R Divider
2 LSB of the 10-bit R divider.
5 - 4
-
Reserved
The values read from these bits are always 0. Do not set these bits.
3
PLLRES
PLL Reset Bit
Set this bit to reset the PLL.
Clear this bit to free the PLL and allow enabling.
2-
Reserved
The value read from this bit is always 0. Do not set this bit.
1
PLLEN
PLL Enable Bit
Set to enable the PLL.
Clear to disable the PLL.
0PLOCK
PLL Lock Indicator
Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com