STLC5464 datasheet(17/83 Pages) STMICROELECTRONICS

17 / 83 page

OTSy, OTDMq

DATA

MEMORY

n x 64kb/s

DATA

MEMORY

n x 64kb/s

DOWN STREAM

ITSy, ITDMq

UP STREAM

ITSx,ITDMp

DOWN STREAM

OTSx, OTDMp

UP STREAM

Bidirectional Connection

OTSy, OTDMq

DATA

MEMORY

n x 64kb/s

DOWN STREAM

ITSx,ITDMp

DOWN STREAM

Unidirectional Connection

p, q = 0 to 7

x, y = 0 to 31

Figure 3 : Unidirectional and Bidirectional Connections

OTSy, OTDMq

DATA

MEMORY

n x 64kb/s

DATA

MEMORY

n x 64kb/s

DOWN STREAM

ITSy, ITDMq

UP STREAM

ITSx,ITDMp

DOWN STREAM

OTSx, OTDMp

UP STREAM

OTSV

Loop

Loopback per channel relevant if bidirectional connection has been done.

p, q = 0 to 7

x, y = 0 to 31

Figure 4 : Loop Back

III - FUNCTIONAL DESCRIPTION (continued)

III.1.5 - Delay through the Matrix

III.1.5.1 - Variable Delay Mode

In the variable delay mode, the delay through the

matrix dependson the relative positions of the input

and output time slots in the frame.

So, some limits are fixed :

- the maximum delay is a frame + 2 time slots,

- the minimum delay is programmable.

Three time slots if IMTD = 1, in this case n = 2 in

the formula hereafter or two time slots if

IMTD = 0, in this case n = 1 in the same formula

(see Paragraph ”Switching Matrix Configuration

Reg SMCR (0C)H” on Page 60).

All the possibilities can be ranked in three cases :

a) If OTSy > ITSx + n then the variable delay is :

OTSy - ITSx Time slots

b) If ITSx < OTSy < ITSx + n then the variable delay

is :

OTSy - ITSx + 32 Time slots

c) OTSy < ITSx then the variable delay is :

32 - (ITSx - OTSy) Time slots.

N.B. Rule b) and rule c) are identical.

For n = 1 and n = 2, see Figure 5 on Page 18.

III.1.5.2 - Sequence Integrity Mode

In the sequence integrity mode (SI = 1, bit located

in the Connection Memory), the input time slots are

put out 2 frames later (see Figure 6 on Page 19).

In this case, the delay is definedby a single expres-

sion :

Constant Delay = (32 - ITSx) + 32 + OTSy

So, the delay in sequence integrity mode varies

from 33 to 95 time slots.

STLC5464

17/83

STLC5464 데이터시트(PDF) 17 Page - STMicroelectronics

STLC5464 데이터시트(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

데이터시트 다운로드

링크 URL