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STLC5464 데이터시트(PDF) 40 Page - STMicroelectronics |
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STLC5464 데이터시트(HTML) 40 Page - STMicroelectronics |
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40 / 83 page ![]() V - CLOCK TIMING (continued) V.3 - GCI Interface CH0 CH1 CH7 B1 B2 MON D C/I AE 125 µs t1 t3 Bit 0, Time S lot 0 t3 t7 t7 FS re ce ived by the Multi-HDLC DIN4/5 DOUT4/5 DCLK de livere d by the Multi-HDLC FS CG de livered by the Multi-HDLC DOUT0/7, CB if FSCG is connected to FS DIN0/8 The four Multiplex Configura tion Registers a re a t ze ro (no de lay betwee n F S and Multiplexes ). t6 GCI Ch a nn e l Figure 29 : GCI Synchro Signal delivered by the Multi-HDLC Symbol Parameter Min. Typ. Max. Unit t1 Clock Period if 4096kHz Clock Period if 2048kHz CLOCKA/B Tmin 244 488 CLOCKA/B Tmax ns ns t3 DCLK to FSCG 20 ns t5 Duration FS 244 125000-244 ns t6 DCLK to Data 50pF DCLK to Data 100pF 50 100 ns ns t7 Set-up Time Data/DCLK 20 ns t7 Hold Time Data/DCLK 20 ns STLC5464 40/83 |
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