전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

STLC5466 데이터시트(PDF) 69 Page - STMicroelectronics

부품명 STLC5466
상세설명  64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED
PDF  130 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC5466 데이터시트(HTML) 69 Page - STMicroelectronics

Back Button STLC5466 Datasheet HTML 65Page - STMicroelectronics STLC5466 Datasheet HTML 66Page - STMicroelectronics STLC5466 Datasheet HTML 67Page - STMicroelectronics STLC5466 Datasheet HTML 68Page - STMicroelectronics STLC5466 Datasheet HTML 69Page - STMicroelectronics STLC5466 Datasheet HTML 70Page - STMicroelectronics STLC5466 Datasheet HTML 71Page - STMicroelectronics STLC5466 Datasheet HTML 72Page - STMicroelectronics STLC5466 Datasheet HTML 73Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 69 / 130 page
background image
69/130
STLC5466
For information:
VI.43 - Initiate Block Address Register 2
IBAR2 (74)H
This register concerns the second 32 HDLC Controller 2 named HDLC 2 connected to input6/output6 of
the switching matrix. The Interrupt Queue is common for the first HDLC Controller and for the second
HDLC Controller 2. So this register doesn’t concern the location of the Interrupt Queue.The location of the
Interrupt Queue is found from the contents of the first IBAR1 register (34)H.
The Initiate Block Address (IBA2) is:
The 23 more significant bits define one of 8 Megawords. (One word comprises two bytes.)
The least significant bit defines one of two bytes when the microprocessor selects one byte.
Example: MHDLC device address inside
µP mapping = 100000H
Initiate Block for HDLC2 address inside
µP mapping = 310000H
IBAR2 value = (310000 - 100000)/256 = 2100H
LT2
LT1
LT0
NCAS latency
BL2
BL1
BL0
Burst Length
WT=0
Burst Length
WT=1
0
0
0
R
000
1
1
0
0
1
1
001
2
2
0
1
0
2
010
4
4
0
1
1
3
011
8
8
1
0
0
R
100
R
R
1
0
1
R
101
R
R
1
1
0
R
110
R
R
1
1
1
R
1
1
1
Full page
R
T,S,R :
These three bits define the SDRAM circuit organisation (1word=2bytes))
bit15
bit8
bit7
bit0
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
After reset (0000)H
A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the
external memory in the MHDLC address space).The offset is zero (A0 to A7 =”0”).
23
87
0
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A9
A8
0
0
0
0
0
0
0
0
tt
TS
R
SDRAM circuit organization
(and shared RAM organization)
If refresh
0
0
0
(1Mx16) SDRAM circuit; shared RAM up to 4M words
2048 cycles / 32ms
0
0
1
(2Mx8) SDRAM circuit; shared RAM up to 8M words
4096 cycles / 64ms
0
1
0
(8Mx8) SDRAM circuit; shared RAM up to 8M words
4096 cycles / 64ms
0
1
1
(4Mx16) SDRAM circuit; shared RAM up to 8M words
4096 cycles / 64ms
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com