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STLC5466 데이터시트(PDF) 83 Page - STMicroelectronics |
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STLC5466 데이터시트(HTML) 83 Page - STMicroelectronics |
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83 / 130 page ![]() 83/130 STLC5466 1 FIGURES associated with text Figure 1-1: MHDLC Block diagramL 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 D7 GCI0 GCI1 V10a V10a GCI0 GCI1 TX GCI V10b DIN 9 DIN 8 CB1 EC1 CB2 EC2 7 D6 V10a V10b V10b SWITCHING MATRIX n x 64 kb/s Scrambler/Descrambler for 32 channels Pseudo Random Sequence Analyser Pseudo Random Sequence Generator FIRST 32 RX HDLC with Address Recognition 32 RX DMAC SECOND 32 RX HDLC with Address Recognition 32 RX DMAC SECOND 32 TX HDLC with CSMA CR for Contention Bus 32 TX DMAC FIRST 32 TX HDLC with CSMA CR for Contention Bus 32 TX DMAC BUS ARBITRATION FIRST TIME SLOT ASSIGNER SECOND TIME SLOT ASSIGNER RX GCI Internal Bus Microprocessor interface SDRAM Controller V10a, bit V10 of TADR1 V10b, bit V10 of TADR2 D6, bit of GCR2 D7, bit of GCR1 |
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