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STLC5466 데이터시트(PDF) 70 Page - STMicroelectronics

부품명 STLC5466
상세설명  64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STLC5466 데이터시트(HTML) 70 Page - STMicroelectronics

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VI.44 - Timer Register 2
TIMR2 (7C)H
This programmable Timer Register 2 indicates the period of the Super Frame Synchronisation signal de-
livered by SFS pin (which is an output).
The duration of the signal is 250 microseconds. The minimum programmable period is 500 microseconds.
The clock frequency of the associated counter is the frequency divided by two of FS Frame Synchronisa-
tion signal applied to FS pin (which is an input).
bit15
bit8
bit7
bit0
S3
S2
S1
S0
MS9
MS8
MS7
MS6
MS5
MS4
MS3
MS2
MS1
MS0
MM1
MM0
0 to 15s
0 to 999ms
0 to 3x0.25ms
After reset (0780)H id 480 ms



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