M306V2EEFS datasheet(254/271 Pages) RENESAS

254 / 271 page

Rev.1.40

Oct 06, 2004 page 254 of 269

M306V2ME-XXXFP, M306V2EEFP

(Note)

Note: Calculated according to the BCLK frequency as follows:

Min.

Data input setup time

tsu(DB-RD)

tsu(RDY-BCLK )

Parameter

Symbol

Unit

Max.

Standard

RDY input setup time

Data input hold time

th(RD-DB)

th(BCLK -RDY)

RDY input hold time

HOLD input setup time

tsu(HOLD-BCLK )

HOLD input hold time

th(BCLK-HOLD )

Data input access time (no wait)

tac1(RD-DB)

tac2(RD-DB)

tac3(RD-DB)

Data input access time (with wait)

Data input access time (when accessing multiplex bus area)

td(BCLK-HLDA )

HLDA output delay time

tac1(RD – DB) =

f(BCLK) ✕ 2

– 45

[ns]

tac2(RD – DB) =

f(BCLK) ✕ 2

– 45

3 ✕ 10

[ns]

tac3(RD – DB) =

f(BCLK) ✕ 2

– 45

3 ✕ 10

[ns]

Table 5.7.2 Memory expansion and microprocessor modes (referenced to VCC = 5 V, VSS = 0 V at

Ta = 25 oC unless otherwise specified)

Table 5.7.1 External clock input (referenced to VCC = 5 V, VSS = 0 V at Ta = 25 oC unless otherwise

specified)

Max.

Min.

External clock input cycle time

External clock input HIGH pulse width

External clock input LOW pulse width

tw(H)

tw(L)

Parameter

Symbol

Unit

Standard

100

External clock rise time

External clock fall time

5.7 Timing Requirements

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