HD151TS206SS datasheet(14/34 Pages) RENESAS

14 / 34 page

HD151TS206SS

Rev.1.00, Apr.28.2003, page 14 of 34

2C Controlled Register Bit Map (cont.)

Byte15 Control Register

Bit

Description

Contents

Type

Default

Note

PCI_5 Output Frequency

Select Bit

0 = 33.3 MHz , 1 = 25 MHz

R/W

48_24MHz Output

Frequency Select Bit

0 = 48 MHz , 1 = 24 MHz

R/W

SAFE_F# Input mode select

Bit

0 = PWRDWN# input mode

1 = SAFE_F# input mode

Default is PWRDWN# input.

SAFE_F# is active “Low” input.

When SAFE_F# is “Low”, frequency

mode is changed to the predefined

frequency mode.

Predefined frequency mode is selected

by B23[1].

R/W

Clock Divider Control Bit

0 = Normal mode

Clock dividers are changed by Table 5

selection decided B9[5:1]

1 = Over or Down clocking mode

Clock dividers are changed by B15[3:0]

and B16[7:0].

B15[3:0] and B16[7:0] are able to be

changed at B15[4] = 1.

R/W

CPU Divider Control Bit3

R/W

CPU Divider Control Bit2

R/W

CPU Divider Control Bit1

R/W

CPU Divider Control Bit0

0001 = 1/1, 0101 = 1/5, 1001 = 1/9

0010 = 1/2, 0110 = 1/6, 1010 = 1/10

0011 = 1/3, 0111 = 1/7, 1011 = 1/11

0100 = 1/4, 1000 = 1/8

R/W

Byte16 Control Register

Bit

Description

Contents

Type

Default

Note

3V66 / PCI / PCIF Divider

Control Bit3

R/W

3V66 / PCI / PCIF Divider

Control Bit2

R/W

3V66 / PCI / PCIF Divider

Control Bit1

R/W

3V66 / PCI / PCIF Divider

Control Bit0

3V66 divider ratio =

0010 = 1/2, 0110 = 1/6, 1010 = 1/10

0011 = 1/3, 0111 = 1/4, 1011 = 1/11

0100 = 1/4, 1000 = 1/8, 1100 = 1/12

0101 = 1/5, 1001 = 1/9

PCI / PCIF divider ratio = 3V66 x 1/2

R/W

SRC Divider Control Bit3

R/W

SRC Divider Control Bit2

R/W

SRC Divider Control Bit1

R/W

SRC Divider Control Bit0

0001 = 1/1, 0101 = 1/5, 1001 = 1/9

0010 = 1/2, 0110 = 1/6, 1010 = 1/10

0011 = 1/3, 0111 = 1/7, 1011 = 1/11

0100 = 1/4, 1000 = 1/8

R/W

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