HD151TS206SS datasheet(18/34 Pages) RENESAS

부품명	HD151TS206SS

상세설명	Mother Board Clock Generator for Intel P4 Chipset (Springdale)

PDF	34 Pages

Scroll/Zoom	100%

제조업체	RENESAS [Renesas Technology Corp]

홈페이지	http://www.renesas.com

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18 / 34 page

HD151TS206SS

Rev.1.00, Apr.28.2003, page 18 of 34

2C Controlled Register Bit Map (cont.)

Byte23 Control Register

Bit

Description

Contents

Type

Default

Note

Watchdog Enable Control Bit

0 = Disable, Pin22 = 3V66_0 output

1 = Enable, Pin22 = RESET# output

R/W

RESET# Reverse Control Bit

0 = Normal , 1 = Reverse

R/W

Watchdog Timer Count Bit3

R/W

Watchdog Timer Count Bit2

R/W

Watchdog Timer Count Bit1

R/W

Watchdog Timer Count Bit0

These 4 bits corresponds to how many

watchdog timer will wait from becoming

“Alarm mode” (B23[0] = 1) to outputting

RESET# pin to “Low”.

Default is 586ms x8 = 4.7s at Power

R/W

Backup Frequency Select Bit

0 = B10[4:0], 1 = B11[4:0]

When SAFE_F# is “Low” , frequency

mode is changed to the predefined

frequency mode decided by B10[4:0] or

B11[4:0].

R/W

Watchdog Status Bit

0 = Normal mode, 1 = Alarm mode

R/W

Byte24 Control Register

Bit

Description

Contents

Type

Default

Note

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

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