HD151TS206SS

Rev.1.00, Apr.28.2003, page 22 of 34

Renasas clock generator I

2. Read mode

2.1

Controller (host) sends a start bit.

2.2

Controller (host) sends the write address D2 (h).

2.3

Renasas clock generator will acknowledge (Renasas clock gen. sends “Low”).

2.4

Controller (host) sends a begin byte M.

2.5

Renasas clock generator will acknowledge (Renasas clock gen. sends “Low”).

2.6

Controller (host) sends a restart bit.

2.7

Controller (host) sends the read address D3 (h).

2.8

Renasas clock generator will acknowledge (Renasas clock gen. sends “Low”).

2.9

Renasas clock generator will send the byte count N.

2.10 Controller (host) will acknowledge.

2.11 Renasas clock generator will send data from byte M to byte M+N–1.

2.12 When Renasas clock generator sends the last byte, controller (host) will not acknowledge.

2.13 Controller (host) sends a stop bit.

Start bit

1 bit

1 bit 1 bit

1 bit

1 bit

7 bits

8 bits

7 bits

1 bit

Restart bit

Slave

address

Slave

address

R/W

D2(h)

R/W

D3(h)

Ack

1 bit

Ack

1 bit

Ack

1 bit

Ack

1 bit

Ack

Ack

Begin Count = N

8 bits

1 bit

1 bit

Stop bit

8 bits

Byte M+N–1

8 bits

8 bits

Byte M

Byte M+1

Not Ack

Begin Byte = M

Notes: 1.

Renasas clock generator is a slave/receiver, I

the latches for the verification.

2.

The data transfer rate supported by this clock generator is 100k bits/sec or less (standard

mode).

3.

The input is operating at 3.3 V logic levels.

4.

The data byte format is 8 bit bytes.

5.

To simplify the clock generator I

the controller.

6.

The bytes must be accessed in sequential order from lowest to highest byte with the ability to

stop after any complete byte has been transferred. The data is loaded until a stop sequence is

issued.

7.

At power-on, all registers are set to a default condition, as shown.