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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DS72011RB120FPV 데이터시트(PDF) 48 Page - Renesas Technology Corp |
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DS72011RB120FPV 데이터시트(HTML) 48 Page - Renesas Technology Corp |
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48 / 1196 page  Section 2 CPU Rev. 2.00 Sep. 07, 2007 Page 20 of 1164 REJ09B0321-0200 2.1.2 Control Registers The control registers consist of four 32-bit registers: the status register (SR), the global base register (GBR), the vector base register (VBR), and the jump table base register (TBR). The status register indicates instruction processing states. The global base register functions as a base address for the GBR indirect addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception handling vector area (including interrupts). The jump table base register functions as the base address of the function table area. 31 0 1 T S 2 3 4 5 6 7 8 9 I[3:0] Q M 13 14 CS BO Status register (SR) 31 0 GBR Global base register (GBR) 31 VBR Vector base register (VBR) 0 31 TBR Jump table base register (TBR) 0 Figure 2.2 Control Registers (1) Status Register (SR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 RRRRRRRRRRRRRRRR 000000 — — 111100 — — R R/W R/W R R R R/W R/W R/W R/W R/W R/W R R R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W: ———————————————— — BO CS — — — M Q I[3:0] — — S T |
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