M32C83T datasheet(69/527 Pages) RENESAS

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Page 46

5. Reset

)

(

Pin States

CNVSS = VCC

CNVSS = VSS

BYTE = VSS

BYTE = VCC

Pin Name

P2, P3, P4

P50

P51

P52

P53

P54

P55

P56

P57

Input port (high-impedance)

Data input (high-impedance)

Address output (indeterminate)

BCLK output

RAS output

WR output (output "H")

RD output (output "H")

RDY input (high-impedance)

Input port (high-impedance)

BHE output (indeterminate)

HLDA output (output value depends on an input to HOLD pin)

HOLD input (high-impedance)

Input port (high-impedance)

NOTES:

1. Ports P11 to P15 are provided in the 144-pin package.

P6 to P15 (1)

____________

Table 5.1 Pin States while RESET Pin is Held "L"

5.2 Software Reset

When the PM03 bit in the PM0 register is set to "1" (microcomputer reset), pins, the CPU and SFR are

reset. Then the microcomputer executes the program from an address determined by the reset vector.

When software reset is performed, some registers in the SFR are not reset. Refer to 4. SFR for details.

Set the PM03 bit to "1" while the main clock is selected as the CPU clock and the main clock oscillation is

stable.

5.3 Watchdog Timer Reset

The microcomputer resets pins, the CPU and the SFR when the watchdog timer underflows while the

CM06 bit in the CM0 register is set to "1" (reset). Then the microcomputer executes the program from an

address indicated by the reset vector.

When watchdog timer reset is performed, some registers in the SFR are not reset. Refer to 4. SFR for

details. Because the PM01 to PM00 bits in the PM0 register are not reset, the processor mode remains

unchanged.

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