M32C83T datasheet(83/527 Pages) RENESAS

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Page 60

7. Bus

)

(

Figure 7.4 External Bus Operation with Software Wait State (1)

Output

Input

Address

Bus cycle(1)

(2) Separate Bus with 1 Wait State

BCLK

Read Signal

Write Signal

Data Bus

Address Bus(2)

Chip-Select Signal(2, 3)

BCLK

Read Signal

Data Bus

Chip-Select Signal(2, 3)

Data Output

Address

Address Bus(2)

Address

Input

(3) Separate Bus with 2 Wait States

Write Signal

BCLK

Read Signal

Write Signal

Address Bus(2)

Address

Bus cycle(1)

(1) Separate Bus with No Wait State

Output

Data Bus

Chip-Select Signal(2, 3)

Input

Bus cycle(1)

Address

NOTES:

1. This example illustrates bus cycle length. Read cycle and write cycle may occur consecutively.

2. The address bus and chip-select signal may be extended depending on CPU state such as an

instruction queue buffer.

3. When the microcomputer continuously accesses the same external space (same CS area), the chip-

select signal may be output continuously.

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