M32C83T datasheet(101/527 Pages) RENESAS

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Page 78

8. Clock Generation Circuit

)

(

Figure 8.12 External Circuit with PLL Frequency Synthesizer

Table 8.2 Bit Settings to Use PLL Clock as CPU Clock Source

PLC0 Register

PLC1 Register

f(XIN)

PLL Clock

PLC02

PLC01

PLC00

PLC12

30 MHz

10MHz

20 MHz

32MHz

8MHz

21.3MHz

Microcomputer

VCONT

VSS

P86

NOTES:

1. Connect VSS to GND via C1 and C2 with shortest possible

wiring. Ground pattern must be formed around the circuit.

2. Optimal values of the low pass filter circuit element,

connected to the VCONT pin, varies with environment

(e.g.noise). Evaluate not only with these optimal values, but

also with other values, to determine the values most

appropriate for your system.

Use capacitors for temperature compensation.

C1=220pF, C2=0.1 µF, R1=1 k

Ω(2)

Use PLL clock as CPU clock source

Set the PLC11 bit to "1"

(PLL clock division enabled)

Set the PLC02 to PLC00 bits

and the PLC12 bit

Set the CM17 bit to "1"

(PLL clock as CPU clock source)

PLC11 and PLC12 bits : Bit in PLC1 register

PLC00 to PLC02 bits, PLC07 bit : Bits in PLC0 register

CM17 bit : Bit in CM1 register

Set the PLC07 bit to "1"

(PLL on)

Wait 20 to 50ms

End

Figure 8.13 Procedure to Use PLL Clock as CPU Clock Source

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