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R8C2K 데이터시트(PDF) 146 Page - Renesas Technology Corp |
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R8C2K 데이터시트(HTML) 146 Page - Renesas Technology Corp |
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146 / 471 page ![]() R8C/2K Group, R8C/2L Group 15. Watchdog Timer Rev.1.10 Dec 21, 2007 Page 129 of 450 REJ09B0406-0110 Figure 15.1 Block Diagram of Watchdog Timer Internal reset signal (“L” active) Write to WDTR register Set to 7FFFh(1) PM12 = 1 Watchdog timer reset PM12 = 0 Watchdog timer interrupt request CSPRO: Bit in CSPR register WDC7: Bit in WDC register PM12: Bit in PM1 register CM07: Bit in CM0 register NOTE: 1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set. 1/128 1/2 CM07 = 1 Prescaler CSPRO = 0 fOCO-S CSPRO = 1 1/16 CM07 = 0, WDC7 = 0 CM07 = 0, WDC7 = 1 CPU clock Watchdog timer |
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