R8C2K datasheet(149/471 Pages) RENESAS

149 / 471 page

R8C/2K Group, R8C/2L Group

15. Watchdog Timer

Rev.1.10

Dec 21, 2007

Page 132 of 450

REJ09B0406-0110

15.1

Count Source Protection Mode Disabled

The count source of the watchdog timer is the CPU clock when count source protection mode is disabled.

Table 15.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled).

NOTES:

1. The watchdog timer is reset when 00h is written to the WDTR register before FFh. The prescaler is

reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused by the

prescaler.

2. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address

0FFFFh with a flash programmer.

Table 15.2

Watchdog Timer Specifications (with Count Source Protection Mode Disabled)

Item

Specification

Count source

CPU clock

Count operation

Decrement

Period

Division ratio of prescaler (n) × count value of watchdog timer (32768)(1)

CPU clock

n: 16 or 128 (selected by WDC7 bit in WDC register)

Example: When the CPU clock frequency is 16 MHz and prescaler

divided by 16, the period is approximately 32.8 ms

Reset condition of watchdog

timer

• Reset

• Write 00h to the WDTR register before writing FFh

• Underflow

Count start condition

The WDTON bit(2) in the OFS register (0FFFFh) selects the operation

of the watchdog timer after a reset

• When the WDTON bit is set to 1 (watchdog timer is in stop state after

reset)

The watchdog timer and prescaler stop after a reset and the count

starts when the WDTS register is written to

• When the WDTON bit is set to 0 (watchdog timer starts automatically

after exiting)

The watchdog timer and prescaler start counting automatically after a

reset

Count stop condition

Stop and wait modes (inherit the count from the held value after exiting

modes)

Operation at time of underflow

• When the PM12 bit in the PM1 register is set to 0

Watchdog timer interrupt

• When the PM12 bit in the PM1 register is set to 1

Watchdog timer reset (Refer to 5.6 Watchdog Timer Reset.)

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