R8C2K datasheet(318/471 Pages) RENESAS

318 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 301 of 450

REJ09B0406-0110

Figure 16.139 TRDOCR Register in PWM3 Mode

Timer RD Output Control Register

(1)

Symbol

Address

After Reset

TRDOCR

013Dh

00h

Bit Symbol

Bit Name

Function

NOTES:

2. If the pin function is set for w aveform output (refer to Tables 16.26 and 16.27), the initial output level is output w hen

the TRDOCR register is set.

TOA1

TOB1

TRDIOD1 initial output level

select bit

TRDIOB1 initial output level

select bit

TOC1

TRDIOC1 initial output level

select bit

These bits are disabled in PWM3 mode.

TRDIOC0 initial output level

select bit

Write to the TRDOCR register w hen both bits TSTART0 and TSTART1 in the TRDSTR register are set to 0 (count

stops).

TOC0

TRDIOA1 initial output level

select bit

TRDIOD0 initial output level

select bit

TOD1

TOB0

TRDIOA0 output level select

bit(2)

0 : Active level “H”,

initial output “L”,

output “H” at compare match w ith the

TRDGRA1register,

output “L” at compare match w ith the

TRDGRA0 register

1 : Active level “L”,

initial output “H”,

output “L” at compare match w ith the

TRDGRA1register,

output “H” at compare match w ith the

TRDGRA0 register

TRDIOB0 output level select

bit(2)

0 : Active level “H”,

initial output “L”,

output “H” at compare match w ith the

TRDGRB1register,

output “L” at compare match w ith the

TRDGRB0 register

1 : Active level “L”,

initial output “H”,

output “L” at compare match w ith the

TRDGRB1register,

output “H” at compare match w ith the

TRDGRB0 register

b7 b6 b5 b4 b3 b2

TOD0

b1 b0

TOA0

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