HD6432351 datasheet(455/1025 Pages) RENESAS

455 / 1025 page

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Sep 15, 2006 page 421 of 988

REJ09B0330-0300

Bits 7, 6, 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the

TCNT counter clearing source.

Channel

Bit 7

CCLR2

Bit 6

CCLR1

Bit 5

CCLR0

Description

0, 3

TCNT clearing disabled

(Initial value)

TCNT cleared by TGRA compare match/input

capture

TCNT cleared by TGRB compare match/input

capture

TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*

TCNT clearing disabled

TCNT cleared by TGRC compare match/input

capture*

TCNT cleared by TGRD compare match/input

capture*

TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*

Channel

Bit 7

Reserved*

Bit 6

CCLR1

Bit 5

CCLR0

Description

1, 2, 4, 5

TCNT clearing disabled

(Initial value)

TCNT cleared by TGRA compare match/input

capture

TCNT cleared by TGRB compare match/input

capture

TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*

Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.

2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the

buffer register setting has priority, and compare match/input capture does not occur.

3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be

modified.

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