HD6432351 datasheet(456/1025 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Sep 15, 2006 page 422 of 988

REJ09B0330-0300

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.

When the input clock is counted using both edges, the input clock period is halved (e.g.

φ/4 both

edges =

φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is

ignored and the phase counting mode setting has priority.

Bit 4

CKEG1

Bit 3

CKEG0

Description

Count at rising edge

(Initial value)

Count at falling edge

—

Count at both edges

Note: Internal clock edge selection is valid when the input clock is

φ/4 or slower. This setting is

ignored if the input clock is

φ/1, or when overflow/underflow of another channel is selected.

Bits 2, 1, and 0—Time Prescaler 2, 1, and 0 (TPSC2 to TPSC0): These bits select the TCNT

counter clock. The clock source can be selected independently for each channel. Table 10.4 shows

the clock sources that can be set for each channel.

Table 10.4 TPU Clock Sources

Internal Clock

External Clock

Overflow/

Underflow

on Another

Channel

φφφφ/1 φφφφ/4 φφφφ/16 φφφφ/64 φφφφ/256 φφφφ/1024 φφφφ/4096 TCLKA TCLKB TCLKC TCLKD Channel

Legend:

Setting

Blank: No setting

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