HD6432351 datasheet(849/1025 Pages) RENESAS

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Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 815 of 988

REJ09B0330-0300

B.2

Functions

MRA—DTC Mode Register A

H'F800–H'FBFF

DTC

SM1

Undefined

—

SM0

Undefined

—

DM1

Undefined

—

DM0

Undefined

—

MD1

Undefined

—

Undefined

—

MD0

Undefined

—

DTS

Undefined

—

Bit

Initial value

Read/Write

Source Address Mode

—

Destination Address Mode

—

DTC Mode

Normal mode

Repeat mode

Block transfer mode

—

DTC Data

Transfer Size

Byte-size

transfer

DTC Transfer Mode Select

Word-size

transfer

Destination side is repeat

area or block area

Source side is repeat area

or block area

DAR is incremented after a transfer

(by +1 when Sz = 0; by +2 when Sz = 1)

DAR is decremented after a transfer

(by -1 when Sz = 0; by -2 when Sz = 1)

DAR is fixed

SAR is incremented after a transfer

(by +1 when Sz = 0; by +2 when Sz = 1)

SAR is decremented after a transfer

(by -1 when Sz = 0; by -2 when Sz = 1)

SAR is fixed

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