HD6432351 datasheet(855/1025 Pages) RENESAS

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Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 821 of 988

REJ09B0330-0300

TIOR3L—Timer I/O Control Register 3L

H'FE83

TPU3

TGR3D I/O Control

TGR3C

is output

compare

TRG3C I/O Control

Output disabled

0 output at compare match

1 output at compare match

Toggle output at compare match

Notes:

Note: When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer

generated.

Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.

IOD3

R/W

IOD2

R/W

IOD1

R/W

IOD0

R/W

IOC3

R/W

IOC0

R/W

IOC2

R/W

IOC1

R/W

Bit

Initial value

Read/Write

Initial output is

0 output

Output disabled

0 output at compare match

1 output at compare match

Toggle output at compare match

Initial output is 1

output

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Capture input

source is

TIOCC3 pin

TGR3C

is input

capture

Capture input

source is channel

4/count clock

Input capture at TCNT4 count-up/

count-down

TGR3D

is output

compare

Output disabled

0 output at compare match

1 output at compare match

Toggle output at compare match

Initial output is 0

output

Output disabled

0 output at compare match

1 output at compare match

Toggle output at compare match

Initial output is 1

output

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Capture input

source is

TIOCD3 pin

TGR3D

is input

capture

Capture input

source is channel

4/count clock

Input capture at TCNT4 count-up/

count-down*1

1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and

φ/1 is used as the TCNT4 count clock,

this setting is invalid and input capture is not generated.

2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid

and input capture/output compare is not generated.

Legend: *: Don’t care

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