HD6432351 datasheet(859/1025 Pages) RENESAS

859 / 1025 page

Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 825 of 988

REJ09B0330-0300

TCR4—Timer Control Register 4

H'FE90

TPU4

TCNT clearing disabled

TCNT cleared by TGRA compare match/input capture

TCNT cleared by TGRB compare match/input capture

Counter Clear

Clock Edge

—

Count at rising edge

Count at falling edge

Count at both edges

Internal clock: counts on

φ/1

Internal clock: counts on

φ/4

Internal clock: counts on

φ/16

Internal clock: counts on

φ/64

External clock: counts on TCLKA pin input

External clock: counts on TCLKC pin input

Internal clock: counts on

φ/1024

Counts on TCNT5 overflow/underflow

Timer Prescaler

—

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Bit

Initial value

Read/Write

Note: This setting is ignored when channel 4 is in phase

counting mode.

Note: * Synchronous operating setting is performed by setting

the SYNC bit TSYR to 1.

Note: This setting is ignored when channel

4 is in phase counting mode.

TCNT cleared by counter clearing for another channel

performing synchronous clearing/synchronous operation*

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