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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HD6432351 데이터시트(PDF) 1019 Page - Renesas Technology Corp |
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HD6432351 데이터시트(HTML) 1019 Page - Renesas Technology Corp |
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1019 / 1025 page  Appendix F Timing of Transition to and Recovery from Hardware Standby Mode Rev. 3.00 Sep 15, 2006 page 985 of 988 REJ09B0330-0300 Appendix F Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 states before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay from STBY low to RES high: 0 ns or more). STBY RES t2 ≥ 0 ns t1 ≥ 10 tcyc Figure F.1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high to execute a power-on reset. STBY RES tOSC tNMIRH t ≥ 100 ns NMI Figure F.2 Timing of Recovery from Hardware Standby Mode |
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