HD6432351 datasheet(139/1025 Pages) RENESAS

139 / 1025 page

Section 5 Interrupt Controller

Rev. 3.00 Sep 15, 2006 page 105 of 988

REJ09B0330-0300

Vector Address*

Interrupt Source

Origin of

Interrupt

Source

Vector

Number

Normal

Mode

Advanced

Mode

IPR

Priority

ERI1 (receive error 1)

H'00A8

H'0150

IPRK6 to 4

High

RXI1 (reception completed 1)

SCI

channel 1 85

H'00AA

H'0154

TXI1 (transmit data empty 1)

H'00AC

H'0158

TEI1 (transmission end 1)

H'00AE

H'015C

Reserved

—

H'00B0

H'00B2

H'00B4

H'00B6

H'0160

H'0164

H'0168

H'016C

IPRK2 to 0

Low

Note:

* Lower 16 bits of the start address.

5.4

Interrupt Operation

5.4.1

Interrupt Control Modes and Interrupt Operation

Interrupt operations in the H8S/2350 Group differ depending on the interrupt control mode.

NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In

the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for

each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt

sources for which the enable bits are set to 1 are controlled by the interrupt controller.

Table 5.5 shows the interrupt control modes.

The interrupt controller performs interrupt control according to the interrupt control mode set by

the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated

by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR.

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