 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
HD6432351 데이터시트(PDF) 140 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD6432351 데이터시트(HTML) 140 Page - Renesas Technology Corp |
|
|
140 / 1025 page  Section 5 Interrupt Controller Rev. 3.00 Sep 15, 2006 page 106 of 988 REJ09B0330-0300 Table 5.5 Interrupt Control Modes SYSCR Interrupt Control Mode INTM1 INTM0 Priority Setting Registers Interrupt Mask Bits Description 0 0 0 — I Interrupt mask control is performed by the I bit. — 1 — — Setting prohibited 2 1 0 IPR I2 to I0 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. — 1 — — Setting prohibited Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt acceptance control 8-level mask control Default priority determination Vector number Interrupt control mode 2 IPR Interrupt source I2 to I0 Interrupt control mode 0 I Figure 5.4 Block Diagram of Interrupt Control Operation |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
