HD6432351 datasheet(237/1025 Pages) RENESAS

237 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 203 of 988

REJ09B0330-0300

7.2.2

I/O Address Register (IOAR)

R/W

Bit

IOAR

Initial value

R/W

*: Undefined

IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source

address or destination address. The upper 8 bits of the transfer address are automatically set to

H'FF.

Whether IOAR functions as the source address register or as the destination address register can

be selected by means of the DTDIR bit in DMACR.

IOAR is invalid in single address mode.

IOAR is not incremented or decremented each time a transfer is executed, so that the address

specified by IOAR is fixed.

IOAR is not initialized by a reset or in standby mode.

7.2.3

Execute Transfer Count Register (ETCR)

ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of

this register is different for sequential mode and idle mode on the one hand, and for repeat mode

on the other.

(1) Sequential Mode and Idle Mode

R/W

Bit

ETCR

Initial value

R/W

Transfer Counter

*: Undefined

In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range

of 1 to 65536). ETCR is decremented by 1 each time a transfer is performed, and when the count

reaches H'0000, the DTE bit in DMABCR is cleared, and transfer ends.

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