HD6432351 datasheet(239/1025 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 205 of 988

REJ09B0330-0300

7.2.4

DMA Control Register (DMACR)

DTSZ

R/W

DTID5

R/W

RPE

R/W

DTDIR

R/W

DTF3

R/W

DTF0

R/W

DTF2

R/W

DTF1

R/W

Bit

DMACR

Initial value

R/W

DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel.

DMACR is initialized to H'00 by a reset, and in standby mode.

Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.

Bit 7

DTSZ

Description

Byte-size transfer

(Initial value)

Word-size transfer

Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of

MAR every data transfer in sequential mode or repeat mode.

In idle mode, MAR is neither incremented nor decremented.

Bit 6

DTID

Description

MAR is incremented after a data transfer

(Initial value)

• When DTSZ = 0, MAR is incremented by 1 after a transfer

• When DTSZ = 1, MAR is incremented by 2 after a transfer

MAR is decremented after a data transfer

• When DTSZ = 0, MAR is decremented by 1 after a transfer

• When DTSZ = 1, MAR is decremented by 2 after a transfer

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