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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HD6432351 데이터시트(PDF) 260 Page - Renesas Technology Corp |
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HD6432351 데이터시트(HTML) 260 Page - Renesas Technology Corp |
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260 / 1025 page  Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 226 of 988 REJ09B0330-0300 Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME bit to 1. Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1 transfer break interrupt. Bit 3 DTIE1B Description 0 Transfer break interrupt disabled (Initial value) 1 Transfer break interrupt enabled Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0 transfer break interrupt. Bit 1 DTIE0B Description 0 Transfer break interrupt disabled (Initial value) 1 Transfer break interrupt enabled |
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