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HD64F2149YV 데이터시트(PDF) 414 Page - Renesas Technology Corp

부품명 HD64F2149YV
상세설명  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV 데이터시트(HTML) 414 Page - Renesas Technology Corp

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Section 13 Timer Connection
Rev. 3.00 Jan 18, 2006 page 386 of 1044
REJ09B0280-0300
Bits 3 to 0—Input Synchronization Signal Inversion (HFINV, VFINV, HIINV, VIINV):
These bits select inversion of the input phase of the spare horizontal synchronization signal
(HFBACKI), the spare vertical synchronization signal (VFBACKI), the horizontal
synchronization signal and composite synchronization signal (HSYNCI, CSYNCI), and the
vertical synchronization signal (VSYNCI).
Bit 3
HFINV
Description
0
The HFBACKI pin state is used directly as the HFBACKI input
(Initial value)
1
The HFBACKI pin state is inverted before use as the HFBACKI input
Bit 2
VFINV
Description
0
1
The VFBACKI pin state is used directly as the VFBACKI input
(Initial value)
The VFBACKI pin state is inverted before use as the VFBACKI input
Bit 1
HIINV
Description
0
The HSYNCI and CSYNCI pin states are used directly as the HSYNCI and CSYNCI
inputs
(Initial value)
1
The HSYNCI and CSYNCI pin states are inverted before use as the HSYNCI and
CSYNCI inputs
Bit 0
VIINV
Description
0
The VSYNCI pin state is used directly as the VSYNCI input
(Initial value)
1
The VSYNCI pin state is inverted before use as the VSYNCI input



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