HD64F2149YV datasheet(452/1075 Pages) RENESAS

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Section 14 Watchdog Timer (WDT)

Rev. 3.00 Jan 18, 2006 page 424 of 1044

REJ09B0280-0300

14.5.5

Counter Value in Transitions between High-Speed Mode, Subactive Mode, and

Watch Mode

If the mode is switched between high-speed mode and subactive mode or between high-speed

mode and watch mode when WDT1 is used as a realtime clock counter, an error will occur in the

counter value when the internal clock is switched.

When the mode is switched from high-speed mode to subactive mode or watch mode, the

increment timing is delayed by approximately 2 or 3 clock cycles when the WDT1 control clock is

switched from the main clock to the subclock.

Also, since the main clock oscillator is halted during subclock operation, when the mode is

switched from watch mode or subactive mode to high-speed mode, the clock is not supplied until

internal oscillation stabilizes. As a result, after oscillation is started, counter incrementing is halted

during the oscillation stabilization time set by bits STS2 to STS0 in SBYCR, and there is a

corresponding discrepancy in the counter value.

Caution is therefore required when using WDT1 as the realtime clock counter.

No error occurs in the counter value while WDT1 is operating in the same mode.

14.5.6

OVF Flag Clear Condition

To clear OVF flag in WOVI handling routine, read TCSR when OVF=1, then write with 0 to

OVF, as stated above.

When WOVI is masked and OVF flag is poling, if contention between OVF flag set and TCSR

read is occurred, OVF=1 is read but OVF can not be cleared by writing with 0 to OVF.

In this case, reading TCSR when OVF=1 two times meet the requirements of OVF clear condition.

Please read TCSR when OVF=1 two times before writing with 0 to OVF.

LOOP

BTST.B

#7,@TCSR

; OVF flag read

BEQ

LOOP

; if OVF=1, exit from loop

MOV.B

@TCSR,R0L

; OVF=1 read again

MOV.W

#H'A521,R0

; OVF flag clear

MOV.W

R0,@TCSR

;

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