HD64F2149YV datasheet(467/1075 Pages) RENESAS

467 / 1075 page

Section 15 Serial Communication Interface (SCI, IrDA)

Rev. 3.00 Jan 18, 2006 page 439 of 1044

REJ09B0280-0300

Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from

TDR to TSR and the next serial data can be written to TDR.

Bit 7

TDRE

Description

[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and writes data to TDR

[Setting conditions]

(Initial value)

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR and data can be written to TDR

Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.

Bit 6

RDRF

Description

[Clearing conditions]

(Initial value)

• When 0 is written in RDRF after reading RDRF = 1

• When the DTC is activated by an RXI interrupt and reads data from RDR

[Setting condition]

When serial reception ends normally and receive data is transferred from RSR to RDR

Note:

RDR and the RDRF flag are not affected and retain their previous values when an error is

detected during reception or when the RE bit in SCR is cleared to 0.

If reception of the next data is completed while the RDRF flag is still set to 1, an overrun

error will occur and the receive data will be lost.

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