HD64F2149YV datasheet(663/1075 Pages) RENESAS

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 635 of 1044

REJ09B0280-0300

MSTPCRL Bit 0—Module Stop (MSTP0): Specifies host inteface (HIF:LPC) module stop

mode.

MSTPCRL

Bit 0

MSTP0

Description

HIF:LPC module stop mode is cleared

HIF:LPC module stop mode is set

(Initial value)

18B.3

Operation

18B.3.1 Host Interface Activation

The host interface is activated by setting at least one of HICR0 bits LPC3E to LPC1E (bits 7 to 5)

to 1 in single-chip mode. When the host interface is activated, the related I/O ports (ports 37 to 30,

ports 83 and 82) function as dedicated host interface input/output pins. In addition, setting the

FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O ports (ports 81 and 80, ports

B0 and B1) to the host interface’s input/output pins.

Use the following procedure to activate the host interface after a reset release.

1. Read the signal line status and confirm that the LPC module can be connected. Also check that

the LPC module is initialized internally.

2. When using channel 3, set LADR3 to determine the channel 3 I/O address and whether two-

way registers are to be used.

3. Set the enable bit (LPC3E to LPC1E) for the channel to be used.

4. Set the enable bits (GA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be

used.

5. Set the selection bits for other functions (SDWNE, IEDIR).

6. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, OBF). Read IDR or TWR15

to clear IBF.

7. Set interrupt enable bits (IBFIE3 to IBFIE1, ERRIE) as necessary.

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