HD64F2149YV datasheet(665/1075 Pages) RENESAS

665 / 1075 page

Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 637 of 1044

REJ09B0280-0300

I/O Read Cycle

I/O Write Cycle

State

Count

Contents

Drive

Source

Value

(3 to 0)

Contents

Drive

Source

Value

(3 to 0)

Start

Host

0000

Start

Host

0000

Cycle type/direction

Host

0000

Cycle type/direction

Host

0010

Address 1

Host

Bits 15 to

Address 1

Host

Bits 15 to

Address 2

Host

Bits 11 to 8

Address 2

Host

Bits 11 to 8

Address 3

Host

Bits 7 to 4

Address 3

Host

Bits 7 to 4

Address 4

Host

Bits 3 to 0

Address 4

Host

Bits 3 to 0

Turnaround

(recovery)

Host

1111

Data 1

Host

Bits 3 to 0

Turnaround

None

ZZZZ

Data 2

Host

Bits 7 to 4

Synchronization

Slave

0000

Turnaround

(recovery)

Host

1111

Data 1

Slave

Bits 3 to 0

Turnaround

None

ZZZZ

Data 2

Slave

Bits 7 to 4

Synchronization

Slave

0000

Turnaround

(recovery)

Slave

1111

Turnaround

(recovery)

Slave

1111

Turnaround

None

ZZZZ

Turnaround

None

ZZZZ

The timing of the

LFRAME, LCLK, and LAD signals is shown in figures 18B.2 and 18B.3.

ADDR

Start

LFRAME

LAD3 to LAD0

Number of clocks

LCLK

TAR

Sync

Data

TAR

Start

Cycle type,

direction,

and size

Figure 18B.2 Typical

LFRAME

LFRAME Timing

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