HD64F2149YV datasheet(769/1075 Pages) RENESAS

769 / 1075 page

Section 23 Clock Pulse Generator

Rev. 3.00 Jan 18, 2006 page 741 of 1044

REJ09B0280-0300

External Clock: The external clock signal should have the same frequency as the system clock

(

φ).

Table 23.4 and figure 23.6 show the input conditions for the external clock.

Table 23.4

External Clock Input Conditions

CC = 2.7 to 3.6 V

Item

Symbol

Min

Max

Unit

Test Conditions

External clock input low pulse width

EXL

—

Figure 23.6

External clock input high pulse width

EXH

—

External clock rise time

EXr

—

External clock fall time

EXf

—

Clock low pulse width

0.4

0.6

cyc

φ ≥ 5 MHz Figure 25.4

—

φ < 5 MHz

Clock high pulse width

0.4

0.6

cyc

φ ≥ 5 MHz

—

φ < 5 MHz

tEXH

tEXL

tEXr

tEXf

VCC × 0.5

EXTAL

Figure 23.6 External Clock Input Timing

Table 23.5 shows the external clock output settling delay time, and figure 23.7 shows the external

clock output settling delay timing. The oscillator and duty adjustment circuit have a function for

adjusting the waveform of the external clock input at the EXTAL pin. When the prescribed clock

signal is input at the EXTAL pin, internal clock signal output is fixed after the elapse of the

external clock output settling delay time (t

DEXT). As the clock signal output is not fixed during the

DEXT period, the reset signal should be driven low to maintain the reset state.

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