HD64F2149YV datasheet(794/1075 Pages) RENESAS

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Section 24 Power-Down State

Rev. 3.00 Jan 18, 2006 page 766 of 1044

REJ09B0280-0300

24.8

Watch Mode

24.8.1

Watch Mode

If a SLEEP instruction is executed in high-speed mode or subactive mode when the SSBY in

SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1)

is set to 1, the CPU makes a transition to watch mode.

In this mode, the CPU and all on-chip supporting modules except WDT1 stop. As long as the

prescribed voltage is supplied, the contents of some of the CPU’s internal registers and on-chip

RAM are retained, and I/O ports retain their states prior to the transition.

24.8.2

Clearing Watch Mode

Watch mode is cleared by an interrupt (WOVI1 interrupt, NMI pin, or pin

IRQ0 to IRQ2, IRQ6,

IRQ7), or by means of the RES pin or STBY pin.

Clearing with an Interrupt: When an interrupt request signal is input, watch mode is cleared and

a transition is made to high-speed mode or medium-speed mode if the LSON bit in LPWRCR is

cleared to 0, or to subactive mode if the LSON bit is set to 1. When making a transition to high-

speed mode, after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are

supplied to the entire chip, and interrupt exception handling is started.

Watch mode cannot be cleared with an IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt if the

corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if

acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by

the CPU.

See section 24.6.3, Setting Oscillation Settling Time after Clearing Software Standby Mode, for

the oscillation settling time setting when making a transition from watch mode to high-speed

mode.

Clearing with the

RES

RES Pin: See “Clearing with the RES Pin” in section 24.6.2, Clearing

Software Standby Mode.

Clearing with the

STBY

STBY Pin: When the STBY pin is driven low, a transition is made to hardware

standby mode.

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