HD64F2149YV datasheet(796/1075 Pages) RENESAS

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Section 24 Power-Down State

Rev. 3.00 Jan 18, 2006 page 768 of 1044

REJ09B0280-0300

24.10

Subactive Mode

24.10.1

Subactive Mode

If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON

bit in LPWRCR, and the PSS bit in TCSR (WDT1) are all set to 1, the CPU makes a transition to

subactive mode. When an interrupt is generated in watch mode, if the LSON bit in LPWRCR is

set to 1, a transition is made to subactive mode. When an interrupt is generated in subsleep mode,

a transition is made to subactive mode.

In subactive mode, the CPU performs sequential program execution at low speed on the subclock.

In this mode, all on-chip supporting modules except TMR0, TMR1, WDT0, and WDT1 stop.

When operating the device in subactive mode, bits SCK2 to SCK0 in SBYCR must all be cleared

to 0.

24.10.2

Clearing Subactive Mode

Subsleep mode is cleared by a SLEEP instruction, or by means of the

RES pin or STBY pin.

Clearing with a SLEEP Instruction: When a SLEEP instruction is executed while the SSBY bit

in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR

(WDT1) is set to 1, subactive mode is cleared and a transition is made to watch mode. When a

SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the LSON bit in

LPWRCR is set to 1, and the PSS bit in TCSR (WDT1) is set to 1, a transition is made to subsleep

mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the

DTON bit is set to 1 and the LSON bit is cleared to 0 in LPWRCR, and the PSS bit in TCSR

(WDT1) is set to 1, a transition is made directly to high-speed mode.

Fort details of direct transition, see section 24.11, Direct Transition.

Clearing with the

RES

RES Pin: See “Clearing with the RES Pin” in section 24.6.2, Clearing

Software Standby Mode.

Clearing with the

STBY

STBY Pin: When the STBY pin is driven low, a transition is made to hardware

standby mode

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