H8SXSLASH1663M datasheet(338/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 306 of 1468

REJ09B0412-0200

9.11

Synchronous DRAM Interface

In this LSI, area 2 in the external space can be used as the SDRAM interface space. Up to 8

Mbytes (64 Mbits) of DRAM is directly connected via the SDRAM interface. The CAS latency

with 2 to 4 is supported.

9.11.1

Setting SDRAM space

Area 2 can be specified as the SDRAM space by the DRAME and DTYPE bits in DRAMCR.

Table 9.24 lists the relationship among the DRAME and DTYPE bits and area 2 interfaces.

In the SDRAM space, pins PB2, PB3, and PB4 are used as the

RAS, CAS, and WE signals. The

PB1 pin is used as the

CS2 signal by the PFCR setting, and the PB5 pin is used as the CKE signal

by setting the OEE bit in DRAMCR to 1. The bus settings of the SDRAM space depend on area 2

settings. The pin wait and program wait for the SDRAM space are not available. For PFCR, see

section 13, I/O Ports.

An SDRAM command is designated by the combination of the

RAS, CAS, and WE signals and

the precharge-sel command (Precharge-sel) output on the upper column address.

This LSI supports the following commands: the NOP, auto-refresh (REF), self-refresh (SELF), all-

bank-precharge (PALL), bank active (ACTV), read (READ), write (WRIT), and mode register

setting (MRS). Commands controlling a bank are not supported.

Table 9.24

Relationship among DRAME and DTYPE and Area 2 Interfaces

DRAME

DTYPE

Area 2 Interface

Basic bus space (initial state)/byte-control SRAM space

DRAM space

SDRAM space

[Legend]

X: Don't care

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