H8SXSLASH1663M datasheet(554/1504 Pages) RENESAS

554 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 522 of 1468

REJ09B0412-0200

Bus cycle

EDACK of

current channel

ETEND of

current channel

Transfer request of

another channel

EDREQ

Last transfer cycle

Bus release

EXDMAC single

transfer cycle

EXDMAC single

transfer cycle

EXDMAC single

transfer cycle

EXDMAC cycle of

another channel

Bus

release

Figure 11.42 Auto-Request/Normal Transfer Mode/Burst Mode

(Conflict with Another Channel/Single Address Mode)

EXDMA

Internal space

EXDMA

CPU

EXDMA

CPU

EXDMA

Bus cycle

CPU operation

External space

Figure 11.43 External Bus Master Cycle Steal Function (Auto-Request/Normal Transfer

Mode/Burst Mode with CPU Cycles/Single Address Mode/EBCCS = 1)

(3)

External Request/Normal Transfer Mode/Cycle Steal Mode

In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a

transfer request is accepted. The next transfer request is accepted after the end of a one-transfer-

unit EXDMA cycle. For external bus space CPU cycles, at least one bus cycle is generated before

the next EXDMA cycle.

If a transfer request is generated for another channel, an EXDMA cycle for the other channel is

generated before the next EXDMA cycle.

The

EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The

same applies to transfer request acceptance and transfer start timing.

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