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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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H8SX/1663M 데이터시트(PDF) 556 Page - Renesas Technology Corp |
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H8SX/1663M 데이터시트(HTML) 556 Page - Renesas Technology Corp |
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556 / 1504 page  Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Sep. 24, 2008 Page 524 of 1468 REJ09B0412-0200 B φ EDREQ EDRAK EDACK Start of transfer by internal edge confirmation Start of transfer by internal edge confirmation Start of transfer by internal edge confirmation Bus release EXDMAC single transfer cycle EXDMAC single transfer cycle EDREQ acceptance internal processing state CPU operation Start of high level sensing Start of high level sensing Start of high level sensing Bus release Bus release EXDMAC single transfer cycle Figure 11.46 External Request/Normal Transfer Mode/Cycle Steal Mode (No Conflict/Single Address Mode/Falling Edge Sensing) 3 cycles B φ EDRAK of another channel Bus release EXDMAC transfer cycle EXDMA read EXDMA write EXDMA read EXDMA write Transfer cycles of another channel EDREQ of another channel EDREQ of current channel EDRAK of current channel Bus cycle Figure 11.47 External Request/Normal Transfer Mode/Cycle Steal Mode (Conflict with Another Channel/Dual Address Mode/Low Level Sensing) |
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