H8SXSLASH1663M datasheet(141/1504 Pages) RENESAS

부품명	H8SX/1663M

상세설명	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 5 Voltage Detection Circuit (LVD)

Rev. 2.00 Sep. 24, 2008 Page 109 of 1468

REJ09B0412-0200

5.3

Voltage Detection Circuit

5.3.1

Voltage Monitoring Reset

Figure 5.2 shows the timing of a voltage monitoring reset by the voltage-detection circuit.

When Vcc falls below Vdet in the state where the LVDE bit in LVDCR has been set to 1 and the

LVDRI bit has been cleared to 0, the LVDF bit is set to 1 and the voltage-detection circuit

generates a voltage monitoring reset.

Next, after Vcc has risen above Vdet, release from the voltage-monitoring reset takes place after a

period for stabilization (t

por) has elapsed. The period for stabilization (tpor) is a time that is generated

by the voltage detection circuit in order to stabilize the Vcc and the internal circuit of the LSI.

When a voltage-monitoring reset is generated, the LVDF bit is set to 1.

For details, see section 30, Electrical Characteristics.

Vdet

Vpor

LVDE

LVDRI

Internal

reset signal

(Low)

Stabilization time (t

POR)

Vcc

↓Write 1

↓Write 0

Figure 5.2 Timing of the Voltage-Monitoring Reset

H8SX/1663M 데이터시트(PDF) 141 Page - Renesas Technology Corp