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H8SX/1663M 데이터시트(PDF) 143 Page - Renesas Technology Corp |
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H8SX/1663M 데이터시트(HTML) 143 Page - Renesas Technology Corp |
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143 / 1504 page ![]() Section 5 Voltage Detection Circuit (LVD) Rev. 2.00 Sep. 24, 2008 Page 111 of 1468 REJ09B0412-0200 IER.IRQ14E = write 0 LVDCR.LVDRI = write 1 LVDCR.LVDE = write 1 PFCRB.ITS14 = write 1 ISR.IRQ14F = clear Clear RSTSR.LVDF * IER.IRQ14E = write 1 ISCR setting (IRQ14SR = 0, IRQ14SF = 1) LVDCR. LVDMON = 1 (Vcc low) (Vcc high) No Yes Note: * When the LVDF cannot be cleared despite Vcc being at a higher electrical potential than Vdet (LVDMON = 1), the voltage-detection circuit is in the state of waiting for stabilization. Clear the bit again after the stabilization time (t POR) has elapsed. Start program Processing for lowered Vcc Interrupt generation when a low voltage is detected Voltage monitoring interrupt (IRQ14) disabled Voltage detection and IRQ register settings If the flag has been set to 1 before the voltage-monitoring interrupt is enabled, clear it by writing 0 after having read it as 1. Voltage-monitoring interrupt (IRQ14) enabled Processing for lowered Vcc Figure 5.4 Example of the Procedure for Setting the Voltage-Monitoring Interrupt |
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