H8SXSLASH1663M datasheet(142/1504 Pages) RENESAS

부품명	H8SX/1663M

상세설명	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 5 Voltage Detection Circuit (LVD)

Rev. 2.00 Sep. 24, 2008 Page 110 of 1468

REJ09B0412-0200

5.3.2

Voltage Monitoring Interrupt

Figure 5.3 shows the timing of a voltage monitoring interrupt by the voltage-detection circuit.

When Vcc falls below the Vdet in a state where the LVDE and LVDRI bits in LVDCR are both

set to 1, the LVDF bit is set to 1 and a voltage monitoring interrupt is requested.

The voltage monitoring interrupt signal is internally connected to

IRQ14-B, so the IRQ14F bit in

the ISR is set to 1 when the interrupt is generated.

As for the IRQ14 setting, set both the ITS14 bit in PFCRB and the IRQ14E bit in the IER to 1, and

the IRQ14SR and IRQ14SF bits in the ISCR to 01 (interrupt request on falling edge).

Figure 5.4 shows the procedure for setting the voltage-monitoring interrupt.

Vdet

Vpor

LVDE

LVDRI

Stabilization time (t

POR)

Vcc

↓Write 1

LVDF

Set

Voltage-monitoring

interrupt signal

(IRQ14)

IRQ14F

Voltage-monitoring

signal

Write 0 after

reading as 1

Figure 5.3 Timing of the Voltage-Monitoring Interrupt

H8SX/1663M 데이터시트(PDF) 142 Page - Renesas Technology Corp