7641 datasheet(77/385 Pages) RENESAS

77 / 385 page

Rev.2.00

Aug 28, 2006

page 60 of 113

7641 Group

REJ09B0336-0200

HARDWARE

FUNCTIONAL DESCRIPTION

Fig. 54 Interrupt request circuit of data bus buffer

MASTER CPU BUS INTERFACE

The 7641 group internally has a 2-byte bus interface which control

signals from the host CPU side can operate (slave mode).

This bus interface allows the 7641 group to be directly connected

with a R/W type of CPU bus or a RD and WR separated type of

CPU bus. Figure 56 shows the block diagram of master CPU bus

interface function.

The data bus buffer function I/O pins (P52 – P57, P6, P72–P74)

also function as the normal I/O ports. When the Master CPU Bus

Interface Enable bit of Data Bus Buffer Control Register (bit 6 of

address 004A16) is “0”, these pins become the normal I/O ports.

When it is “1”, these pins become the master CPU bus interface

function pins.

Additionally, when using the master CPU bus interface function,

set port P6 to input mode by setting “0016” into its port direction

The selection of either the single data bus buffer mode, which

uses 1 byte: data bus buffer 0 only, or the double data bus buffer

mode, which uses 2 bytes: data bus buffer 0 and data bus buffer

1, is performed by the Data Bus Buffer Function Select Bit of Data

Bus Buffer Control Register 1 (bit 7 of address 004E16). Port P72

becomes S1 input pin in the double data bus buffer mode.

When data is written from the host CPU side, an input buffer full

interrupt occurs. When data is read from the host CPU, an output

buffer empty interrupt occurs. The 7641 group shares two input

buffer full interrupt requests and two output buffer empty interrupt

requests as shown in Figure 54, respectively.

The 7641 group can also operate the master CPU bus interface

connecting with the Built-in DMAC. This could transfer a large

amount of data fast.

An input signal level of data bus buffer function input pins can be

selected between a CMOS level and a TTL level. Set it using the

Master CPU Bus Input Level Select Bit of Port Control Register

(address 001016)

Input buffer

full flag 0

IBF0

Input buffer

full flag 1

IBF1

Rising edge

detection circuit

One-shot pulse

generating circuit

One-shot pulse

generating circuit

Input buffer full interrupt

request signal IBF

Output buffer

full flag 0

OBF0

Output buffer

full flag 1

OBF1

One-shot pulse

generating circuit

One-shot pulse

generating circuit

Output buffer empty interrupt

request signal OBE

Interrupt request is set at this rising edge

IBF0

IBF1

IBF

OBF0

(

OBE0)

OBF1

(

OBE1)

OBE

OBE0

OBE1

Rising edge

detection circuit

Rising edge

detection circuit

Rising edge

detection circuit

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