R8CSLASH15 datasheet(161/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 149 of 253

REJ09B0164-0210

15.1

Transfer Clock

A transfer clock can be selected from 7 internal clocks (

φ/256, φ/128, φ/64, φ/32, φ/16, φ/8 and φ/4) and

an external clock.

When using the SSU, set the SCKS bit in the SSMR2 register to “1” and select the SSCK pin as the

serial clock pin.

When the MSS bit in the SSCRH register is set to “1” (operates as master device), an internal clock can

be selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs clocks

of the transfer rate selected in the CKS0 to CKS2 bits in the SSCRH register.

When the MSS bit in the SSCRH register is set to “0” (operates as slave device), an external clock can

be selected and the SSCK pin functions as input.

15.1.1

Association between Transfer Clock Polarity, Phase and Data

Association between transfer clock polarity, phase and data changes according to a combination of the

SSUMS bit in the SSMR2 register and the CPHS and CPOS bits in the SSMR register. Figure 15.9

shows the Association between Transfer Clock Polarity, Phase and Transfer Data.

Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR

to “0”, transfer is started from the MSB to LSB.

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