R8CSLASH15 datasheet(163/277 Pages) RENESAS

163 / 277 page

R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 151 of 253

REJ09B0164-0210

15.2

SS Shift Register (SSTRSR)

The SSTRSR register is the shift register to transmit and receive the serial data.

When the transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit

in the SSMR register is set to “0” (MSB-first), the bit 0 in the SSTDR register is transferred to the bit 0 in

the SSTRSR register. When the MLS bit is set to “1” (LSB-first), the bit 7 in the SSTDR register is

transferred to the bit 0 in the SSTRSR register.

15.2.1

Association between Data I/O Pin and SS Shift Register

Connecting association between the data I/O pin and SSTRSR register (SS shift register) changes

according to a combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2

Figure 15.10 shows a Connecting Association between Data I/O Pin and SSTRSR Register.

Figure 15.10

Connecting Association between Data I/O Pin and SSTRSR Register

SSTRSR Register

SSO

SSI

• When SSUMS=0

(clock synchronous communication mode)

SSTRSR Register

SSO

SSI

• When SSUMS=1 (4-wire bus communication mode),

BIDE=0 (standard mode) and MSS=0 (operates as

slave device)

SSTRSR Register

SSO

SSI

• When SSUMS=1 (4-wire bus communication mode),

BIDE=0 (standard mode) and MSS=1 (operates as

master device)

SSTRSR Register

SSO

SSI

• When SSUMS=1 (4-wire bus communication mode),

BIDE=1 (bidirectional mode)

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