SH7708 datasheet(446/633 Pages) RENESAS

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Bit 2n + 1 (n = 0–7): Port Pull-Up Control (PBnPUP): Controls the pull-up of each bit in the 8-bit

port by means of built-in resistors. This setting is valid even if the port pin is set to output by the

PBnIO bit. Therefore, to avoid unnecessary power consumption and ensure the reliability of the

chip, a pull-up setting should not be made when the corresponding port pin has been set to output.

Bit 2n + 1: PBnPUP Description

Bit n (n = 0–7) of the 8-bit port is pulled up.

(Initial value)

Bit n (n = 0–7) of the 8-bit port is not pulled up.

Bit 2n (n = 0–7)—Port I/O Control (PBnDIR): Controls whether each bit of 8-bit port is an input

or an output.

Bit 2n: PBnIO

Description

Bit n (n = 0–7) of the 8-bit port is an input.

(Initial value)

Bit n (n = 0–7) of the 8-bit port is an output.

15.2.2

Port Data Register (PDTR)

The port data register (PDTR) is an 8-bit read/write register used as data latches for each bit of the

8-bit port. When a bit is set to be used as an output, the value written into PDTR is output from the

external pin. When a value is read from PDTR, the external pin value sampled on the external bus

clock is returned.

PDTR is not initialized by a power-on reset or manual reset, or in standby mode, and it retains its

contents. However, if PDTR is read when a bus release request is issued (when

BREQ is asserted),

its value may not be read correctly. Therefore,

BREQ should not be asserted when reading PDTR.

Bit:

Bit name:

PB7DT

PB6DT

PB5DT

PB4DT

PB3DT

PB2DT

PB1DT

PB0DT

Initial value:

—

R/W:

R/W

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