SH7708 datasheet(85/633 Pages) RENESAS

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3.4.3

MMU Instruction (LDLTB)

The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is

0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR

to the value specified by PTEH and PTEL, using VPN bits 16–12 specified in PTEH as the index

number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16–12 specified in PTEH and

ASID bits 4–0 in PTEH are used as the index number.

Figure 3.9 shows the case where the IX bit in MMUCR is 0.

When an MMU exception occurs, the virtual page number of the virtual address that caused the

exception is set in PTEH by hardware. The way is set in the RC bit of MMUCR for each exception

according to the rules shown in figure 3.9. Consequently, if the LDTLB instruction is issued after

setting only PTEL in the MMU exception handling routine, TLB entry recording is possible. Any

TLB entry can be updated by software rewriting of PTEH and the RC bits in MMUCR.

As the LDTLB instruction changes address translation information, there is a risk of destroying

address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure,

therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an

access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two

instructions after the LDLTB instruction.

VPN(31–17)

VPN(11–10)

ASID(7–0)

VPN

ASID

VPN

SV 0 0 RC 0 TF IX AT

PPN

0 V 0 PR SZ C D SH 0

Write

PPN(31–10) PR(1–0) SZ C

D SH

Write

Data array

Address array

Way selection

Way 0 to 3

MMUCR

Index

PTEH register

PTEL register

Figure 3.9 Operation of LDTLB Instruction

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